1. Field of the Invention
This invention relates to a semiconductor memory device and a manufacturing method thereof and, more particularly, to a nonvolatile memory device having a plurality of cell word lines arranged at extremely narrow pitches as is represented by a NAND flash memory.
2. Description of the Related Art
For example, in the case of a NAND flash memory, a more inexpensive nonvolatile memory device is realized by setting the chip size to minimum. That is, a lowering in the cost of the NAND flash memory is realized by using a memory cell array form in which a plurality of NAND strings (NAND memory units) are arranged in an array form. In this case, each NAND string is configured by a preset number of flash memory cells (NAND cells) and two selection gate transistors arranged to sandwich the preset number of flash memory cells. Further, in the case of a memory cell array form, since contact holes are not arranged between cell word lines that are connected to control gate electrodes of the flash memory cells having the stacked gate structures, it is advantageous that the cell word lines can be arranged at extremely narrow pitches in minimizing the chip size.
NAND flash memories are accepted in the market and the market scale is significantly enlarged. Further, in order to meet the demand of the market, a nonvolatile memory device with higher density is realized by enhancing the performance of a processing exposure device and developing a memory cell array that is miniaturized to the limit of exposure of the exposure device.
For example, in the conventional NAND flash memory, the NAND strings are miniaturized to the limit of exposure of the exposure device used for resist-processing a line pattern of the cell word lines. That is, the distance A between the adjacent cell word lines, the width B of the cell word line and the distance C between the selection gate line and the cell word line that lies adjacent to the selection gate line are respectively miniaturized to the limit of exposure of the exposure device and are often set to the same value (A=B=C).
However, in miniaturizing the NAND strings and miniaturizing the memory cell array, an example that threatens the reliability of the cell is reported (for example, see Jae-Duk Lee, “A new programming disturbance phenomenon in NAND flash memory by source/drain hot-electrons generated by GIDL current” IEEE NVSMW 2006 pp. 31 to 33). According to the report, there is disclosed a problem that a defect occurs in which hot-electrons are injected into a floating gate electrode corresponding to a cell word line adjacent to the selection gate line on the source side by a gate-induced drain leakage (GIDL) current caused by potential transferred to the selection gate line arranged on the source side at the data write operation time and data is destroyed. In order to solve the problem, it is supposed that it is indispensable to enlarge the distance between the selection gate line on the source side configuring the NAND string and the cell word line adjacent thereto to approximately 110 nm. However, this condition (C>A=B, C≧110 nm) harms the relation (A=B=C) in the miniaturization process at the exposure limit.
Further, if the distance (C) between the selection gate line on the source side and the cell word line adjacent thereto is enlarged without limitation, it is known that an exposure focus margin for resist-processing is reduced by the limitation of the lithography technology. It is the known fact that light from the light source that passes through an opening portion of the mask has a constant wavelength (for example, 193 nm in the case of an ArF ray) and is applied to the mask with constant light intensity. In the case of a non-repetitive pattern, it becomes difficult to realize the stable resist-process due to disturbance of the light intensity. That is, if the selection gate line on the source side is arranged to harm the repetitiveness of the cell word line adjacent thereto (C>A=B), it becomes impossible to miniaturize a resist used to process the selection gate lines and cell word lines to the limit of exposure of the exposure device.
A lowering in the exposure focus margin makes formation of the cell word lines and selection gate lines unstable. Particularly, disturbance in the process of the cell word lines in the width direction causes the threshold value (Vth) distribution width to be enlarged after writing or erasing of the flash memory cell and thus the manufacturing yield and the reliability of the NAND flash memory may be reduced.